Reduced scaling or shrinking of the geometries of devices used in integrated semiconductor circuit technology for forming denser circuits has required voltage supply sources to provide lower voltages than the heretofore generally accepted standard supply voltage of 5 volts so as to avoid a voltage breakdown in the insulation layers of the smaller devices. During the transition from 5 volt supplies to the lower voltage supplies of, say, 3.3 volts, a mix of circuits is being used wherein some of the circuits haee been designed for use with standard 5 volt supplies while other circuits have been designed for use with the lower 3.3 volt supplies. In general, the geometries of memory circuits are reduced at a faster rate than are the geometries of logic circuits which are coupled to the memory circuits. In particular, complementary metal oxide semiconductor (CMOS) random access memories are currently being designed in about 3.3 volt supply technology, whereas logic circuits, such as those of the transistor-transistor logic (TTL) type, which receive the output signals or data from the memories, are still being designed in a 5 volt supply technology. With these low voltage memory circuits feeding into the high voltage logic circuits through off-chip drivers, excessive voltage stress is encountered in the thin insulation or oxide layers of some of the devices in the off-chip drivers which form the interface between the memory and logic circuits, and, furthermore, undesirable current leakage paths are created therein resulting in a power loss and also at times in serious CMOS latch up problems. It is known that the upper limit of gate oxide field strength, e.g., of silicon dioxide, is about 3 megavolts per centimeter and, therefore, the maximum allowable voltage across a gate oxide of about 150 angstroms thickness which is often used today in low voltage technology devices is approximately 4.5 volts.
In U.S. Pat. No. 4,585,958, filed Dec. 30, 1983, there is disclosed a CMOS driver circuit having a P-channel pull up device and an N channel pull down device with a NAND circuit and a NOR circuit connected to the gate electrodes of the pull up and pull down devices, respectively.
U.S. Pat. No. 4,217,502, filed Sept. 11, 1978 discloses a circuit similar to that of the hereinabove identified U.S. Pat. No. 4,585,958 but additionally provides voltage control of the P-channel transistor substrate.
U.S. Pat. No. 4,574,273, filed Nov. 4, 1983, discloses a voltage converter circuit which uses two power supply voltages, one at +5 volts and another at +21 volts.